Thin film transistors art elements widely used for switching elements of liquid crystal displays, wherein a thin film transistor switches a liquid crystal display by controlling current flowing between the source/drain according to the voltage applied to the gate electrode.
A thin film transistor mostly uses polycrystal silicon film or amorphous silicon film for the semiconductor layer, and for resistive contact i.e., ohmic contact between the semiconductor layer and the source/drain electrodes, a semiconductor layer having impurity ions injected therein in provided between the semiconductor layer and the source/drain regions.
FIGS. 1(a) to 1(f) show conventional processes for fabricating a staggered, hydrogen embrittled amorphous thin film transistor.
A first metal film is deposited on a cleaned glass substrate 1, which is subjected to a patterning with photoetching process to form source/drain electrodes 2 and 3 as shown in FIG. 1(a).
For ohmic contact, a semiconductor layer 6 serving as an active layer is formed over the source/drain electrodes 2 and 3 by forming a high density n+type amorphous silicon film doped with phosphor(n+a-Si) 4 on the exposed surfaces of the patterned source/drain electrodes 2 and 3 as shown in FIG. 1(b), depositing a hydrogen embrittled amorphous silican(a-Si:H) film 5 on all over the using a PECVD(Plasma Enhanced Chemical Vapor Deposition) equipment as shown in FIG. 1(c), and patterning the hydrogen embrittled amorphous silicon film(FIG. 1(d)).
Then, finally a conventional staggered thin film transistor can be formed by forming a gate insulation film 7 on all over the surface(FIG. 1(e)), forming a second metal film on the gate insulation film 7, and carrying out patterning of the second metal film with a photootching process to form a gate electrode 8 on the gate insulation film 7 over the active layer 6(FIG. 1(f)).
However, in the foregoing conventional method for fabricating a thin film transistor, the active layer 6 has been formed by depositing a hydrogen embrittled amorphous silicon using a PECVD equipment at a temperature lower than that of the gate insulation film 7, i.e., the forming temperature of the gate insulation film 7 is higher than that of the active layer 6. Therefore, in the process for forming the gate insulation film at a higher temperature, there has been a limit of temperature due to escape of hydrogena from the active layer 6. Accordingly, there has been a problem of deterioration of the element characteristics due to the difficulty in forming a gate insulation film of good quality and the deterioration of the interface between the gate insulation film and the active is layer.
FIGS. 2(a) to 2(f) show conventional processes for forming a hydrogen embrittled amorphous silicon thin film transistor having single gate insulation film.
As shown in FIG. 2(a), first, a gate electrode 12 is formed by forming a first metal film for a gate using a sputter equipment on a cleaned glass substrate 11 and carrying out patterning of the first metal film with a photoetching process.
Then, as shown in FIG. 2(b), a gate insulation film 13 is formed on all over the glass substrate having the gate electrode 12 formed thereon with PECVD method or RPCVD(Remote Plasma Chemical Vapor Deposition) method.
That is, with plasma discharge under the atmosphere of SiH.sub.4, NH.sub.3, N.sub.2 and H.sub.2 gases at in appropriately controlled flow ratio, a silicon nitride(SiNx) film can be formed.
As shown in FIG. 2(c), a hydrogen embrittled amorphous semiconductor layer(a Si:H) 14 is formed using SiH.sub.4 and H.sub.2 gas with PECVD method the same with the method for forming the gate insulation film 13 on the gate insulation film 13, and on which semiconductor layer 14 an impurity injected amorphous semiconductor layer 15 is formed.
As shown in FIG. 2(d), the impurity injected amorphous semiconductor layer 15 and the hydrogen embrittled amorphous semiconductor layer 14 formed by plasma in PECVD or RPCVD method are subjected to a patterning to form their width greater or the same with the width of the gate electrode 12.
As shown in FIG. 2(e), source and drain electrodes 16 and 17 are formed by depositing a second metal film on all over the substrate using a sputter equipment, which is subjected to a patterning to a prefixed pattern with a photoetching process.
In this instant, the second metal film in patterned such that parts 18 of the gate electrode 12 are positioned directly over the source and drain electrodes 16 and 17.
An shown in FIG. 2(f), the exposed, impurity injected amorphous semiconductor layer 15 between the source and the drain electrodes 16 and 17 is removed selectively with dry etching method to form a channel of a thin film transistor.
With the foregoing process, the hydrogen embrittled amorphous semiconductor layer 14 can be exposed between the source/drain electrodes 16 and 17 over the gate electrode 12.
FIG. 3 is a section of a conventional thin film transistor to having a channel protection layer.
The conventional thin film transistor having a channel protection layer includes, as shown in FIG. 3, a single gate insulation film 23 farmed on all over a glass substrate 21 so as to cover a gate electrode 22, a semiconductor layer 24 having a wider pattern width than the gate electrode 22 formed on the gate insulation film 23, a channel protection layer 25 having a narrower pattern width than the gate electrode 22 formed on the semiconductor layer 24 directly over the gate electrode 22, an impurity injected semiconductor layer 26 tor making ohmic contact formed on the semiconductor layer 24 so as to cover the channel protection layer 25 except central part of the upper side of the channel protection layer 25, and a source electrode 27 and a drain electrode 28 formed so as to expose the semiconductor layer 24 between them.
The processes for fabricating the foregoing conventional thin film transistor is to be explained hereinafter, referring to FIGS. 4(a) to 4(e).
First, as shown in FIG. 4(a), the gate electrode 22 is formed by depositing a metal layer of, such as Cr, Mo, Al and Ta with sputtering method on the cleaned glass substrate 21 and carrying out a photoetching process.
Then, as shown in FIG. 4(b), the gate insulation film 23, the semiconductor layer 24 and the channel protection layer 25 are deposited successively with PECVD method.
Herein, for the gate insulation layer 23, an SiNx:H film formed using SiH.sub.4, NH.sub.3, N.sub.2 and H.sub.2 gases is used mostly, for the semiconductor layer 24, an a-Si:H film formed using SiH4 and H2 gases is used mostly, and for the channel protection layer 25, an SiNx:H film deposited using SiH.sub.4, NH.sub.3, N.sub.2 and H.sub.2 gases is used mostly.
As shown in FIG. 4(c), patterning is carried out so that the pattern width of the channel protection layer 25 in narrower than the pattern width of the gate electrode 22.
After carrying out the patterning of the channel protection layer 25, an impurity injected semiconductor layer 26 for making ohmic contact, a resitive contact, between the semiconductor layer 24 and source/drain electrodes to be formed in following process, is formed on all over the substrate with PECVD method using SiH.sub.4 and PH.sub.3 gases.
As shown in FIG. 4(d), by carrying out patterning of the impurity injected semiconductor layer 26 and the semiconductor layer 24 such that the pattern widths of theirs are to be greater than that of the gate electrode 22, and as shown in FIG. 4(e), by carrying out a metal layer deposition on all over the substrate and photoetching of it, a source electrode 27 and a drain electrode 28 can be formed.
Finally, a conventional thin film transistor can be completed by exposing the semiconductor layer 24 through etching of the impurity injected semiconductor layer 26 formed on the channel protection layer 25 between the source electrode 27 and the drain electrode 25 with dry etching process.
FIG. 5 is a schematic drawing of a PECVD equipment for forming a conventional gate insulation film or a conventional amorphous semiconductor layer film.
Referring to FIG. 5, an amorphous semiconductor deposition equipment includes a reaction furnace 41, an upper electrode 42 mounted on upper side of the reaction furnace 41, a lower elecetrode 43 mounted at lower side of the reaction furnace 41 opposite to the upper electrode 42 for putting wafers 44 thereon for processing, a high frequency generation power source 45 for applying high frequency voltage to the upper electrode 42, a pumping equipment 46 for maintaining the reaction furnace 41 at vacuum or discharge gas therefrom, and a gas injection part for injecting reaction gases and dilution gases into the reaction furnace 41.
The gas injection part includes a silane gas pipe 49-1 having an MFC(Mass Flow Controller) 47-1 and a shut off valve 48-1 for injecting silane(SiH.sub.4) gas into the reaction furnace 41, a hydrogen gas pipe 49-2 having a MFC 47-2 and a shut off valve 48-2 for injecting hydrogen(H.sub.2) gas into the reaction furnace 41, and a nitrogen gas pipe 49-3 having an MFC 47-3 and a shut off valve 48-3 for injecting nitrogen(N.sub.2) gas into the reaction furnace 41.
The method for forming an amorphous semiconductor film using the foregoing equipment is, at first, to put a wafer(or a sample substrate) 44 on the lower electrode 43 in the reaction furnace 41, produce high vacuum in the reaction furnace 41 by operating the pumping equipment 46, and maintain the pressure in the reaction furnace constant by injecting silane(SiH.sub.4) gas and nitrogen or hydrogen) gas in an appropriate flow ratio into the reaction furnace 41.
In this instant, when the temperature at the lower electrode 43 becomes constant, high frequency voltage is applied to the upper electrode 42.
The plasma formed between the two, upper and lower, electrodes 42 and 43 by the high frequency voltage applied to the upper electrode 42 makes the silane (SiH.sub.4) gas to decompose depositing ions on the wafer 44 under non-thermal equilibrium to form an amorphous semiconductor film thereon.
To obtain a hydrogen embrittled amorphous silicon film from above process, hydrogen, instead of nitrogen, should be injected into the reaction furnace 41 together with silane(SiH.sub.4) gas.
However, with the conventional method for fabricating a thin film transistor using the foregoing PECVD method or RPCVD method, it has been hard to obtain a good quality amorphous semiconductor or a gate insulation file because the semiconductor layer and the gate inselation film should be fabricated urder a high vacuum in a range of 10.sup.-2 Torr which causes generation of plasma in the process of forming a thin film that damages the lower surface of the thin film due to the high energy electrons and ions generated by the plasma, and causes to generate unnecessary decomposed particles.
Due to this, there is a limit in improving the characteristics of a thin film transistor.
Also the method has a problem of low productivity due to use of a high vacuum equipment that requires a long time in loading wafers and establishing a vacuum.
Further, in case a multilayer film is desired to be deposited continuously using this high vacuum thin film deposition method, this method has not only low processing speed but also difficulty in improving productivity and reducing the production cost due to a long deposition period of time required for the separate operation of the vacuum equipment.